An example of the conventional technology is represented in FIG. 3. In a semiconductor tester, an operation clock signal is generated inside the test system. Test patterns are generated in synchronism with the clock signal and applied to a semiconductor device under test. The resultant output signals from the device under test are compared with expected pattern. In such an arrangement, a problem of producing jitters does not occur since all the operation in the system is synchronized with the internal clock signal. On the other hand, there is a semiconductor device which generates a clock signal by itself. In such a case, a method may be used for utilizing the clock signal from the device itself to operate the semiconductor tester. In this method, the internal clock of the semiconductor tester has to be synchronized with the clock signal from the device under test. However, the problem of jitters will occur between the two clocks as shown in FIG. 4 since the two clocks are completely out of synchronization.
Therefore, it is an object of the present invention to solve this problem and to provide a semiconductor tester circuit which will not generate jitters when using an external clock signal.